The majority of present day integrated circuits can be implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. Often, a typical MOS transistor includes a gate electrode as a control electrode formed over a semiconductive substrate, and spaced apart source and drain electrodes within the substrate between which a current can flow. A control voltage applied to the gate electrode may control the flow of current through a channel in the semiconductive substrate between the source and drain electrodes. Usually, dielectric materials, such as silicon dioxide, are commonly employed to electrically separate the various gate electrodes in the integrated circuit.
Typically, the reduction in the size of MOSFETs has provided continued improvement in speed performance, circuit density, and cost per unit function over the past few decades. As the gate length of the conventional bulk MOSFET is reduced, however, the source and drain electrodes increasingly can interact with the channel and gain influence on the channel potential. Consequently, a transistor with a short gate length may suffer from problems related to the inability of the gate electrode to substantially control the on and off states of the channel. Generally, phenomena such as reduced gate control associated with transistors with short channel lengths are termed “short-channel effects.” Increased substrate doping concentration, reduced gate oxide thickness, and shallow source/drain junctions may be ways to suppress short-channel effects. However, for device scaling into the sub-50 nanometer (nm) regime, the requirements for doping concentration, gate oxide thickness, and source/drain doping profiles often become increasingly difficult to meet.
Typically, shrinkage of the length and width of the device is the implemented method for reducing the device footprint. Generally, other solutions such as three-dimensional stacking of multiple physical layers of transistors using several substrates is still in its infancy and has mechanical, positional and thickness issues requiring solutions.
Accordingly, it is desirable to provide methods for fabricating integrated circuits having nanowires. In addition, it is desirable to provide integrated circuits with nanowires to more efficiently utilize the semiconductor substrate and reduce the integrated circuit footprint. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.